A low-power reduced swing global clocking methodology
نویسندگان
چکیده
منابع مشابه
A New Single-Clock Flip-Flop for Half-Swing Clocking
We propose a new flip-flop configuration which saves about 60% of total clocking power using a half-swing clock. To use the half-swing clock, level converters or special clock drivers are traditionally required and the power consumptions of these logic cannot be ignored. In the proposed scheme, only NMOSes are clocked with half-swing clock in order to make it operate without the level converter...
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2004
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2004.826204